The basic DRAM memory technology prevalent in semiconductor applications operates so as to allow immediate write or rewrite of data into cells as soon as the data are valid on the bit lines. As memory chip density has increased, however, power and current density problems have become critical. Modifications to conventional DRAM operation have been proposed to reduce massive bit line charging currents associated with read/write cycles and refresh cycles. Masakaza Aoki et al. described one such technique in a paper in the IEEE Journal of Solid State Circuits, Vol. 24, No. 5, October 1989, pp 1206-1212, "A 1.5 V DRAM for Battery Based Applications." However, they indicate a severe memory cycle time penalty of 100 ns arising mostly from their write or rewrite operations. Another technique described in U.S. Pat. No. 5,414,656, "Low Charge Consumption Memory", issued to Kenney May 9, 1995, can avoid most of the 100 ns penalty, but will incur a similar write penalty if an attractive signal enhancing option is utilized. Since low current, high signal, and rapid write time are desirable attributes for memory products, a need exists for methods which provide all of them simultaneously.